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nmos linear image sensors are self-scanning photodiode arrays designed specifically as detectors for multichannel spectroscopy. the scanning circuit is made up of n-channel mos transistors, operates at low power consumption and is easy to handle. each photodiode has a large active area, high uv sensitivity yet very low noise, delivering a high s/n even at low light levels. nmos linear image sensors also of fer excellent output linearity and wide dynamic range. S3921/s3924 series have a current-integration readout circuit utilizing the video line and an impedance conversion circuit. the output is available in boxcar waveform allowing signal readout with a simple external circuit. the photodiodes of S3921 series have a height of 2.5 mm and are arrayed in a row at a spacing of 50 m. the photodiodes of s392 4 series also have a height of 2.5 mm but are arrayed at a spacing of 25 m. the photodiodes are available in 3 different pixel quantities fo r each series, 128 (S3921-128q), 256 (S3921-256q, s3924-256q) and 512 (S3921-512q, s3924-512q) and 1024 (s3924-1024q). quartz glass is the standar d window material. features l built-in current-integration readout circuit utilizing video line capacitance and impedance conversion circuit (boxcar waveform output) l wide active area pixel pitch: 50 m (S3921 series) 25 m (s3924 series) pixel height: 2.5 mm l high uv sensitivity with good stability l low dark current and high saturation charge allow a long integration time and a wide dynamic range at room temperature l excellent output linearity and sensitivity spatial uniformity l low voltage, single power supply operation l start pulse, clock pulse and video line reset pulse are cmos logic compatible applications l multichannel spectrophotometry l image readout system image sensor nmos linear image sensor voltage output type with current-integration readout circuit and impedance conversion circuit S3921/s3924 series b a 2.5 mm 1.0 m 1.0 m 400 m oxidation silicon p type silicon n type silicon S3921 series: a=50 m, b=45 m s3924 series: a=25 m, b=20 m figure 1 equivalent circuit vss start st clock clock 1 2 address switch address switch active photodiode dummy diode reset switch reset reset v active video vdd end of scan source follower circuit digital shift re gister (mos shift re gister) saturation control gate saturation control drain dummy video figure 2 active area structure

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nmos linear image sensor S3921/s3924 series figure 3 dimensional outlines (unit: mm) S3921-128q, s3924-256q S3921-256q, s3924-512q 0.51 25.4 2.54 3.0 31.75 10.4 5.4 0.2 5.0 0.2 3.2 0.3 active area 6.4 2.5 0.25 10.16 1.3 0.2* photosensitive surface * optical distance from the outer surface of the quartz window to the chip surface 0.51 25.4 2.54 3.0 active area 12.8 2.5 6.4 ?0.3 31.75 10.4 5.4 ?0.2 5.0 ?0.2 0.25 10.16 1.3 ?0.2* photosensitive surface * optical distance from the outer surface of the quartz window to the chip surface S3921-512q, s3924-1024q 0.51 25.4 3.0 40.6 10.4 5.4 ?0.2 5.0 ?0.2 12.8 ?0.3 active area 25.6 2.5 0.25 10.16 1.3 ?0.2 * photosensitive surface * optical distance from the outer surface of the quartz window to the chip surface 2.54 2 1 st vss vscg reset reset v (vscd) vss active video dummy video vsub nc nc nc nc nc nc nc nc nc end of scan vdd 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 vss, vsub and nc should be grounded. figure 4 pin connection kmpdc0025ea kmpda0060ea kmpda0061ea kmpda0062ea
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82 8 8 0 1, ' 8 0 construction of image sensor the nmos image sensor consists of a scanning circuit made up of mos transistors, a photodiode array, and a switching transistor array that addresses each photodiode, all integrated onto a monolithic silicon chip. figure 1 shows the circuit of a nmos linear image sensor. the mos scanning circuit operates at low power consump- tion and generates a scanning pulse train by using a start pulse and 2-phase clock pulses in order to turn on each ad- dress sequentially. each address switch is comprised of an nmos transistor using the photodiode as the source, the video line as the drain and the scanning pulse input section as the gate. the photodiode array operates in charge integration mode so that the output is proportional to the amount of light expo- sure (light intensity integration time). each cell consists of an active photodiode and a dummy diode, which are respectively connected to the active video line and the dummy video line via a switching transistor. each of the active photodiodes is also connected to the saturation control drain via the saturation control gate, so that the photo- diode blooming can be suppressed by grounding the satura- tion control gate. applying a pulse signal to the saturation control gate triggers all reset. (see ?auxiliary functions?.) 10 -5 10 1 10 0 10 -1 10 -2 10 -3 10 -4 10 -4 10 -3 10 -2 10 -1 10 0 output voltage (v) exposure ( lx s) (typ. reset v=2.5 v, vdd=5.0 v, v =5 v, light source: 2856 k) saturation exposure S3921-512q S3921-128q S3921-256q saturation voltage 0.3 0.2 0.1 0 200 400 600 800 1000 1200 wavelength (nm) photo sensitivity (a/w) (ta=25 ?c) 10 -5 10 1 10 0 10 -1 10 -2 10 -3 10 -4 10 -4 10 -3 10 -2 10 -1 10 0 output voltage (v) exposure ( lx s) s3924-1024q s3924-256q saturation voltage (typ. reset v=2.5 v, vdd=5.0 v, v =5 v, light source: 2856 k) s3924-512q saturation exposure kmpdb0149ea kmpdb0118ea kmpdb0119ea figure 5 spectral response (typical example) figure 6 output voltage vs. exposure
nmos linear image sensor S3921/s3924 series figure 2 shows the schematic diagram of the photodiode active area. this active area has a pn junction consisting of an n-type diffusion layer formed on a p-type silicon substrate. a signal charge generated by light input accumulates as a capacitive charge in this pn junction. the n-type diffusion layer provides high uv sensitivity but low dark current. driver circuit a start pulse st and 2-phase clock pulses 1, 2 are needed to drive the shift register. these start and clock pulses are positive going pulses and cmos logic compatible. the 2-phase clock pulses 1, 2 can be either completely separated or complementary. however, both pulses must not be ? high ? at the same time. a clock pulse space (x 1 and x 2 in figure 7) of a ? rise time/fall time - 20 ? ns or more should be input if the rise and fall times of 1, 2 are longer than 20 ns. the 1 and 2 clock pulses must be held at ? high ? at least 200 ns. since the photodiode signal is obtained at the rise of each 2 pulse, the clock pulse frequency will equal the video data rate. the amplitude of start pulse st is the same as the 1 and 2 pulses. the shift register starts the scanning at the ? high ? level of st, so the start pulse interval is equal to signal accu- mulation time. the st pulse must be held ? high ? at least 200 ns and overlap with 2 at least for 200 ns. to operate the shift register correctly, 2 must change from the ? high ? level to the ? low ? level only once during ? high ? level of st. the timing chart for each pulse is shown in figure 7. end of scan the end of scan (eos) signal appears in synchronization with the 2 timing right after the last photodiode is addressed, and the eos terminal should be pulled up at 5 v using a 10 k ? resistor. tvd tpw 1 tpw 2 tf s tr 1 tf 1 x1 x2 t ov ts r-2 tf 2 reset vr (h) vr (l) td r-2 t ovr tfr trr st v s (h) v s (l) v 1 (h) v 1 (l) v 2 (h) v 2 (l) 1 2 end of scan active video output tpw s tr s st 1 2 reset figure 7 timing chart for driver circuit signal readout circuit S3921/s3924 series include a current integration circuit uti- lizing the video line capacitance and an impedance conver- sion circuit. this allows signal readout with a simple external circuit. however, a positive bias must be applied to the video line because the photodiode anode of nmos linear image sensors is at 0 v (vss). this is done by adding an appropriate pulse to the reset terminal. the amplitude of the reset pulse should be equal to 1, 2 and st. when the reset pulse is at the high level, the video line is set at the reset v voltage. figure 8 shows the reset v voltage margin. a higher clock pulse amplitude allows higher reset v voltage and saturation charge. conversely, if the reset v voltage is set at a low level with a higher clock pulse ampli- tude, the rise and fall times of video output waveform can be shortened. setting the reset v voltage to 2.5 v is recom- mended when the amplitude of 1, 2, st and reset is 5 v. to obtain a stable output, an overlap between the reset pulse (reset ) and 2 must be settled. (reset must rise while 2 is at the high level.) furthermore, reset must fall while 2 is at the low level. S3921/s3924 series provide output signals with negative- going boxcar waveform which include a dc offset of approxi- mately 1 v when reset v is 2.5 v. if you want to remove the dc offset to obtain the positive-going output, the signal readout circuit and pulse timing shown in figure 9 are recommended. in this circuit, rs must be larger than 10 k ? . also, the gain is determined by the ratio of rf to rs, so choose the rf value that suits your application. figure 8 reset v voltage margin 4 0 6 8 10 12 45678 10 clock pulse amplitude (v) reset v voltage (v) 2 9 min. reset v voltage range max. recommended reset v voltage kmpdc0026ea kmpdb0047ea
hamamatsu photonics k.k., solid state division 1126-1 ichino-cho, higashi-ku, hamamatsu city, 435-8558 japan, telephone: (81) 53-434-3311, fax: (81) 53-434-5184, www.hamamatsu.com u.s.a.: hamamatsu corporation: 360 foothill road, p.o.box 6910, bridgewater, n.j. 08807-0910, u.s.a., telephone: (1) 908-231-0 960, fax: (1) 908-231-1218 germany: hamamatsu photonics deutschland gmbh: arzbergerstr. 10, d-82211 herrsching am ammersee, germany, telephone: (49) 08152 -3750, fax: (49) 08152-2658 france: hamamatsu photonics france s.a.r.l.: 19, rue du saule trapu, parc du moulin de massy, 91882 massy cedex, france, telephone: 33-(1) 69 53 71 00, fax: 33-(1) 69 53 71 10 united kingdom: hamamatsu photonics uk limited: 2 howard court, 10 tewin road, welwyn garden city, hertfordshire al7 1bw, unit ed kingdom, telephone: (44) 1707-294888, fax: (44) 1707-325777 north europe: hamamatsu photonics norden ab: smidesv ? gen 12, se-171 41 solna, sweden, telephone: (46) 8-509-031-00, fax: (46) 8-509-031-01 italy: hamamatsu photonics italia s.r.l.: strada della moia, 1/e, 20020 arese, (milano), italy, telephone: (39) 02-935-81-733, fax: (39) 02-935-81-741 information furnished by hamamatsu is believed to be reliable. however, no responsibility is assumed for possible inaccuracies or omissions. specifications are subject to change without notice. no patent rights are granted to any of the circuits described herein. ?200 5 hamamatsu photonics k.k. nmos linear image sensor S3921/s3924 series cat. no. kmpd1044e01 oct. 2005 dn vscg vss vsub nc eos eos 10 k +5 v +5 v + e open dummy video active video reset +2.5 v reset v (vscd) + + +15 v rs 10 k rf vdd st 2 1 st 2 1 reset reset st 2 1 anti-blooming function if the incident light intensity is higher than the saturation charge level, even partially, a signal charge in excess of the sa turation charge cannot accumulate in the photodiode. this excessive charge flows out into the video line degrading the signal purity. to avoid this problem and maintain the signal purity, applying the same voltage as the reset v voltage to the saturation control d rain and grounding the saturation control gate are effective. if the incident light intensity is extremely high, a positive bias sho uld be applied to the saturation control gate. the larger the voltage applied to the saturation control gate, the higher the function for suppressing the excessive saturation charge will be. however, this voltage also lowers the amount of saturation charge, so an optimum bias voltage should be selected. auxiliary functions 1) all reset in normal operation, the accumulated charge in each photodiode is reset when the signal is read out. besides this method that uses the readout line, S3921/s3924 series can reset the photodiode charge by applying a pulse to the saturation control gate. the amplitude of this pulse should be equal to the 1, 2, st, reset pulses and the pulse width should be longer than 5 s. when the saturation control gate is set at the ? high ? level, all photodiodes are reset to the saturation control drain potential. conversely, when the saturation control gate is set at the ? low ? level (0 v), the signal charge accumulates in each photodiode without being reset. 2) dummy video S3921/s3924 series have a dummy video line. positive-polarity video signals with the dc offset remove can be obtained by differential amplification of the active video line and dummy video line outputs. when not needed, leave this unconnected. precautions for using nmos linear image sensors 1) electrostatic countermeasures nmos linear image sensors are designed to resist static electrical charges. however, take sufficient cautions and countermea- sures to prevent damage from static charges when handling the sensors. 2) window if dust or grime sticks to the surface of the light input window, it appears as a black blemish or smear on the image. before u sing the image sensor, the window surface should be cleaned. wipe off the window surface with a soft cloth, cleaning paper or cotton swab slightly moistened with organic solvent such as alcohol, and then lightly blow away with compressed air. do not rub the window with dry cloth or cotton swab as this may generate static electricity. kmpdc0027ea kmpdc0028ea !
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